Renesas H8S/2112R Manuals

Manuals and User Guides for Renesas H8S/2112R. We have 1 Renesas H8S/2112R manual available for free PDF download: Hardware Manual

Renesas H8S/2112R Hardware Manual (984 pages)

6-Bit Single-Chip Microcomputer

Brand: Renesas | Category: Computer Hardware | Size: 6.16 MB

Table of Contents
9
Section 1 Overview

27
- Features
  27
  - Applications
    27
  - Overview of Functions
    28
- List of Products
  33
- Block Diagram
  34
- Pin Descriptions
  35
  - Pin Assignments
    35
  - Pin Assignment in each Operating Mode
    38
  - Pin Functions
    45
Section 2 CPU

55
Section 3 MCU Operating Modes

91
- Operating Mode Selection
  91
- Register Descriptions
  92
- Operating Mode Descriptions
  99
  - Mode 2
    99
- Address Map
  99
Section 4 Resets

101
- Types of Resets
  101
- Input/Output Pin
  102
- Register Descriptions
  103
- Pin Reset
  109
- Power-On Reset
  110
- Watchdog Timer Reset
  111
- Determination of Reset Generation Source
  111
Section 5 Exception Handling

113
- Exception Handling Types and Priority
  113
- Exception Sources and Exception Vector Table
  114
- Reset
  117
- Interrupt Exception Handling
  119
- Trap Instruction Exception Handling
  119
- Stack Status after Exception Handling
  120
- Usage Note
  121
Section 6 Interrupt Controller

123
Section 7 Bus Controller (BSC)

173
- Register Descriptions
  173
  - Bus Control Register (BCR)
    173
  - Wait State Control Register (WSCR)
    174
Section 8 I/O Ports

175
- Register Descriptions
  182
- Pin Functions
  191
  - Port 1
    191
  - Port 2
    191
  - Port 3
    192
  - Port 4
    193
  - Port 5
    196
  - Port 6
    197
  - Port 7
    198
  - Port 8
    198
  - Port 9
    201
  - Port a
    202
  - Port B
    203
  - Port C
    206
  - Port D
    210
  - Port E
    211
  - Port F
    212
  - Port G
    214
  - Port H
    218
- Change of Peripheral Function Pins
  219
Section 9 8-Bit PWM Timer (PWMU)

223
- Features
  223
- Input/Output Pins
  225
- Register Descriptions
  226
- Operation
  240
  - Single-Pulse Mode (8 Bits, 12 Bits, and 16 Bits)
    240
  - Pulse Division Mode
    244
- Usage Note
  247
  - Setting Module Stop Mode
    247
  - Note on Using 16-Bit/12-Bit Single-Pulse PWM Timer
    247
Section 10 16-Bit Timer Pulse Unit (TPU)

249
- Features
  249
- Input/Output Pins
  253
- Register Descriptions
  254
  - Timer Control Register (TCR)
    255
  - Timer Mode Register (TMDR)
    259
  - Timer I/O Control Register (TIOR)
    261
  - Timer Interrupt Enable Register (TIER)
    270
  - Timer Status Register (TSR)
    272
  - Timer Counter (TCNT)
    275
  - Timer General Register (TGR)
    275
  - Timer Start Register (TSTR)
    275
  - Timer Synchro Register (TSYR)
    276
- Interface to Bus Master
  277
  - 16-Bit Registers
    277
- Operation
  279
  - Basic Functions
    279
  - Synchronous Operation
    285
  - Buffer Operation
    287
  - PWM Modes
    291
  - Phase Counting Mode
    295
- Interrupts
  300
  - Interrupt Source and Priority
    300
  - A/D Converter Activation
    301
- Operation Timing
  302
  - Input/Output Timing
    302
  - Interrupt Signal Timing
    306
- Usage Notes
  309
Section 11 16-Bit Cycle Measurement Timer (TCM)

317
Section 12 8-Bit Timer (TMR)

341
- Features
  341
- Input/Output Pins
  344
- Register Descriptions
  345
- Operation
  360
  - Pulse Output
    360
- Operation Timing
  361
- TMR_0 and TMR_1 Cascaded Connection
  365
  - 16-Bit Count Mode
    365
  - Compare-Match Count Mode
    365
- TMR_Y and TMR_X Cascaded Connection
  366
  - 16-Bit Count Mode
    366
  - Compare-Match Count Mode
    366
  - Input Capture Operation
    367
- Interrupt Sources
  369
- Usage Notes
  370
Section 13 Watchdog Timer (WDT)

375
- Features
  375
- Input/Output Pins
  377
- Register Descriptions
  377
  - Timer Counter (TCNT)
    378
  - Timer Control/Status Register (TCSR)
    378
- Operation
  382
  - Watchdog Timer Mode
    382
  - Interval Timer Mode
    383
- Interrupt Sources
  384
- Usage Notes
  385
Section 14 Serial Communication Interface (SCI)

387
Section 15 CIR Interface

455
Section 16 Serial Communication Interface with FIFO (SCIF)

481
- Features
  481
- Input/Output Pins
  483
- Register Descriptions
  484
  - Receive Shift Register (FRSR)
    485
  - Receive Buffer Register (FRBR)
    485
  - Transmitter Shift Register (FTSR)
    486
  - Transmitter Holding Register (FTHR)
    486
  - Divisor Latch H, L (FDLH, FDLL)
    486
  - Interrupt Enable Register (FIER)
    487
  - Interrupt Identification Register (FIIR)
    488
  - FIFO Control Register (FFCR)
    490
  - Line Control Register (FLCR)
    491
  - Modem Control Register (FMCR)
    492
  - Line Status Register (FLSR)
    494
  - Modem Status Register (FMSR)
    498
  - Scratch Pad Register (FSCR)
    499
  - SCIF Control Register (SCIFCR)
    500
- Operation
  502
- Interrupt Sources
  516
- Usage Note
  516
  - Power-Down Mode When LCLK Is Selected for SCLK
    516
Section 17 I C Bus Interface (IIC)

517
- Features
  517
- Input/Output Pins
  520
- Register Descriptions
  521
  - C Bus Data Register (ICDR)
    522
  - Slave Address Register (SAR)
    523
  - Second Slave Address Register (SARX)
    524
  - C Bus Mode Register (ICMR)
    526
  - C Bus Control Register (ICCR)
    529
  - C Bus Status Register (ICSR)
    538
  - C Bus Control Initialization Register (ICRES)
    542
  - C Bus Extended Control Register (ICXR)
    543
- Operation
  547
  - C Bus Data Format
    547
  - Initialization
    549
  - Master Transmit Operation
    549
  - Master Receive Operation
    554
  - Slave Receive Operation
    557
  - Slave Transmit Operation
    561
  - IRIC Setting Timing and SCL Control
    564
  - Noise Canceler
    566
  - Initialization of Internal State
    566
- Interrupt Sources
  568
- Usage Notes
  569
  - Module Stop Mode Setting
    572
Section 18 Smbus 2.0 Interface (SMBUS)

573
- Features
  573
- Input/Output Pins
  574
- Register Descriptions
  574
- Operation
  576
  - Smbus 2.0 Data Format
    576
  - Usage of PEC Calculation Module
    577
- Usage Notes
  578
  - Module Stop Mode Setting
    578
Section 19 Keyboard Buffer Control Unit (PS2)

579
- Features
  579
- Input/Output Pins
  581
- Register Descriptions
  582
- Operation
  591
  - Receive Operation
    591
  - Transmit Operation
    593
  - Receive Abort
    594
  - KCLKI and KDI Read Timing
    597
  - KCLKO and KDO Write Timing
    597
  - KBF Setting Timing and KCLK Control
    598
  - Receive Timing
    599
  - Operation During Data Reception
    599
  - KCLK Fall Interrupt Operation
    600
  - 19.4.10 First KCLK Falling Interrupt
    601
- Usage Notes
  605
Section 20 LPC Interface (LPC)

607
Section 21 FSI Interface

673
Section 22 A/D Converter

719
- Features
  719
- Input/Output Pins
  721
- Register Descriptions
  722
- Operation
  727
  - Single Mode
    727
  - Scan Mode
    728
  - Input Sampling and A/D Conversion Time
    729
- Interrupt Source
  730
- A/D Conversion Accuracy Definitions
  731
- Usage Notes
  733
Section 23 RAM

739
Section 24 Flash Memory

741
- Features
  741
- Mode Transition Diagram
  743
- Flash Memory MAT Configuration
  745
- Block Structure
  746
- Programming/Erasing Interface
  747
- Input/Output Pins
  749
- Register Descriptions
  750
  - Programming/Erasing Interface Registers
    752
  - Programming/Erasing Interface Parameters
    758
- On-Board Programming Mode
  769
  - Boot Mode
    769
  - User Program Mode
    773
  - User Boot Mode
    782
  - Storable Areas for On-Chip Program and Program Data
    786
- Protection
  792
  - Hardware Protection
    792
  - Software Protection
    793
  - Error Protection
    793
- Switching between User MAT and User Boot MAT
  795
- Programmer Mode
  796
- Standard Serial Communication Interface Specifications for Boot Mode
  796
- Usage Notes
  824
Section 25 Clock Pulse Generator

827
- Oscillator
  828
  - Connecting Crystal Resonator
    828
  - External Clock Input Method
    829
- Duty Correction Circuit
  831
- Subclock Input Circuit
  832
- Subclock Waveform Forming Circuit
  833
- Clock Select Circuit
  833
- Usage Notes
  834
  - Notes on Resonator
    834
  - Notes on Board Design
    834
Section 26 Power-Down Modes

835
- Register Descriptions
  836
- Mode Transitions and LSI States
  843
- Medium-Speed Mode
  845
- Sleep Mode
  846
- Software Standby Mode
  847
- Watch Mode
  849
- Module Stop Mode
  850
- Usage Notes
  850
  - I/O Port Status
    850
  - Current Consumption When Waiting for Oscillation Stabilization
    850
Section 27 List of Registers

851
Section 28 Electrical Characteristics

941
- Absolute Maximum Ratings
  941
- DC Characteristics
  942
- AC Characteristics
  949
  - Clock Timing
    949
  - Control Signal Timing
    952
  - Timing of On-Chip Peripheral Modules
    954
- A/D Conversion Characteristics
  964
- Flash Memory Characteristics
  965
- Power-On Reset Characteristics
  966
- Usage Notes
  967
Appendix

969
- I/O Port States in each Pin State
  969
- Product Lineup
  970
- Package Dimensions
  971
- Treatment of Unused Pins
  974
Index

975

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Renesas H8S/2112R Manuals

Renesas H8S/2112R Hardware Manual (984 pages)

Table of Contents

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Resets

Section 5 Exception Handling

Section 6 Interrupt Controller

Section 7 Bus Controller (BSC)

Section 8 I/O Ports

Section 9 8-Bit PWM Timer (PWMU)

Section 10 16-Bit Timer Pulse Unit (TPU)

Section 11 16-Bit Cycle Measurement Timer (TCM)

Section 12 8-Bit Timer (TMR)

Section 13 Watchdog Timer (WDT)

Section 14 Serial Communication Interface (SCI)

Section 15 CIR Interface

Section 16 Serial Communication Interface with FIFO (SCIF)

Section 17 I C Bus Interface (IIC)

Section 18 Smbus 2.0 Interface (SMBUS)

Section 19 Keyboard Buffer Control Unit (PS2)

Section 20 LPC Interface (LPC)

Section 21 FSI Interface

Section 22 A/D Converter

Section 23 RAM

Section 24 Flash Memory

Section 25 Clock Pulse Generator

Section 26 Power-Down Modes

Section 27 List of Registers

Section 28 Electrical Characteristics

Appendix

Index

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