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Section 8 I/O Ports
8.2.3
Port 3
(1)
P37/SERIRQ, P36/LCLK, P35/LRESET, P34/LFRAME, P33/LAD3, P32/LAD2,
P31/LAD1, P30/LAD0
The pin function is switched as shown below according to the combination of the FSILIE bit in
SLCR of FSI, and the SCIFE bit in HICR5, the LPC4E bit in HICR4, and the LPC3E to LPC1E
bits in HICR0 of LPC, and the P3nDDR bit. LPCENABLE in the following table is expressed by
the following logical expression.
LPCENABLE = 1: FSILIE + SCIFE + LPC4E + LPC3E + LPC2E + LPC1E
LPCENABLE
P3nDDR
Pin function
Rev. 1.00 May 09, 2008 Page 166 of 954
REJ09B0462-0100
0
0
P3n input pin
1
P3n output pin
1
LPC I/O pin
(n = 7 to 0)
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