Renesas H8S/2100 Series Hardware Manual page 532

2
Section 17 I C Bus Interface (IIC)
Bit Bit Name
1 IRIC
Rev. 1.00 May 09, 2008 Page 506 of 954
REJ09B0462-0100
Initial
Value R/W Description
2
0 R/(W)* I
Indicates that the I
interrupt request to the CPU.
IRIC is set at different times depending on the FS bit in
SAR, the FSX bit in SARX, and the WAIT bit in ICMR.
See section 17.4.7, IRIC Setting Timing and SCL
Control. The conditions under which IRIC is set also
differ depending on the setting of the ACKE bit in
ICCR.
[Setting conditions]
•
1. When a start condition is detected in transmit mode
2. When data is transferred from ICDRT to ICDRS in
3. When data is transferred from ICDRS to ICDRR in
4. If 1 is received as the acknowledge bit (when the
•
1. When a wait is inserted between the data and
2. When the AL flag is set to 1 after bus arbitration is
•
1. When the slave address (SVA or SVAX) matches
2. When the general call address is detected after the
3. When a stop condition is detected (when the STOP
C Bus Interface Interrupt Request Flag
2
C bus interface has issued an
All operating modes:
and the ICDRE flag is set to 1
transmit mode and the ICDRE flag is set to 1
receive mode and the ICDRF flag is set to 1
ACKE bit is 1 in transmit mode) at the completion of
data transmission
2
I C bus format master mode:
acknowledge bit when the WAIT bit is 1
lost while the ALIE bit is 1
2
I C bus format slave mode:
after the reception of the first frame following the
start condition and the AAS flag or AASX flag is set
to 1
reception of the first frame following the start
condition and the ADZ flag is set to 1 (the FS bit in
SAR is 0)
or ESTP flag is set to 1) while the STOPIM bit is 0