Renesas H8S/2100 Series Hardware Manual page 603

Software standby mode
and watch mode
KCLK
(a) Interrupt timing in software standby mode and watch mode
KCLK
Software standby mode
and watch mode
internal signal
Interrupt internal signal
(b) When a transition to software standby mode or watch mode is performed while the KCLI is high
KCLK
Software standby mode
and watch mode
internal signal
Interrupt internal signal
(c) When a transition to software standby mode or watch mode is performed while the KCLK is low
KCLK
Software standby mode
and watch mode
internal signal
Interrupt internal signal
Figure 19.17 Interrupt Timing in Software Standby Mode and Watch Mode
B
PS2
Interrupt
control
Figure 19.16 First KCLK Interrupt Path
Section 19 Keyboard Buffer Control Unit (PS2)
Interrupt control block
Falling edge
detection circuit
Interrupt
vector
generation
A
circuit
1
Interrupt generated
4 5
Interrupt generated
4 5
Interrupt generated
Rev. 1.00 May 09, 2008 Page 577 of 954
Interrupt request
to CPU
2
6
6
REJ09B0462-0100