Renesas H8S/2100 Series Hardware Manual page 680

6-bit single-chip microcomputer
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Section 21 FSI Interface
Bit
Bit Name
6
RE
5
FSITEIE
4
FSIRXIE
3 to 0 
Rev. 1.00 May 09, 2008 Page 654 of 954
REJ09B0462-0100
R/W
Initial
Value
EC
Host Description
0
R/W
0
R/W
0
R/W
All 0
R/W
FSI Reception Enable
Controls FSI reception and indicates reception status
in combination with the LFBUSY bit.
0: FSI reception wait state
[Clearing condition]
When FSI data reception is completed.
1: When LFBUSY = 0: Starts reception.
When LFBUSY = 1: FSI reception is in progress
(automatically set).
FSI Transmit End Interrupt Enable
0: Disables the FSITEI interrupt request.
1: Enables the FSITEI interrupt request.
FSI Receive Interrupt Enable
0: Disables the FSIRXI interrupt request.
1: Enables the FSIRXI interrupt request.
Reserved
The initial value should not be modified.

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