Host Interface Control Registers 2 And 3 (Hicr2 And Hicr3) - Renesas H8S/2100 Series Hardware Manual

Initial
Bit Bit Name Value
0 LSCIB 0
20.3.2

Host Interface Control Registers 2 and 3 (HICR2 and HICR3)

HICR2 controls interrupts to an LPC interface slave (this LSI). The bit 7 in HICR3 and HICR2
monitor the states of the LPC interface pins. Bits 6 to 0 in HICR2 are initialized to H'00 by a reset.
The states of other bits are decided by the pin states. The pin states can be monitored by the pin
monitoring bits regardless of the LPC interface operating state or the operating state of the
functions that use pin multiplexing.
• HICR2
Initial
Bit Bit Name Value
7 GA20 Undefined R
6 LRST 0
5 SDWN 0
R/W
Slave Host Description

R/W LSCI output Bit
Controls LSCI output in combination with the LSCIE bit
IN HICR0. For details, refer to description on the
LSCIE bit in HICR0.
R/W
Slave Host Description

GA20 Pin Monitor
R/(W)* 
LPC Reset Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when an LPC hardware reset occurs.
0: [Clearing condition]
Writing 0 after reading LRST = 1
1: [Setting condition]
LRESET pin falling edge detection
R/(W)* 
LPC Shutdown Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when an LPC hardware shutdown request is
generated.
0: [Clearing conditions]
•
Writing 0 after reading SDWN = 1
•
LPC hardware reset
(LRESET pin falling edge detection)
•
LPC software reset (LRSTB = 1)
1: [Setting condition]
LPCPD pin falling edge detection
Section 20 LPC Interface (LPC)
Rev. 1.00 May 09, 2008 Page 593 of 954
REJ09B0462-0100