Renesas H8S/2100 Series Hardware Manual page 22

20.4.7 SCIF Control from LPC Interface......................................................................... 639
20.5 Interrupt Sources................................................................................................................ 640
20.5.1 IBFI1, IBFI2, IBFI3, IBFI4, OBEI, and ERRI ..................................................... 640
20.5.2 SMI, HIRQ1, HIRQ3, HIRQ4, HIRQ5, HIRQ6, HIRQ7, HIRQ8, HIRQ9,
HIRQ10, HIRQ11, HIRQ12, HIRQ13, HIRQ14, and HIRQ15 ........................... 641
20.6 Usage Note......................................................................................................................... 644
20.6.1 Data Conflict......................................................................................................... 644
Section 21 FSI Interface .................................................................................... 647
21.1 Features.............................................................................................................................. 647
21.2 Input/Output Pins............................................................................................................... 649
21.3 Register Description .......................................................................................................... 650
21.3.1 FSI Control Register 1 (FSICR1) ......................................................................... 652
21.3.2 FSI Control Register 2 (FSICR2) ......................................................................... 653
21.3.3 FSI Byte Count Register (FSIBNR) ..................................................................... 655
21.3.4 FSI Instruction Register (FSIINS) ........................................................................ 656
21.3.5 FSI Instruction Register (FSIRDINS)................................................................... 657
21.3.6 FSI Program Instruction Register (FSIPPINS) ..................................................... 657
21.3.7 FSI Status Register (FSISTR)............................................................................... 657
21.3.8 FSI Transmit Data Registers 0 to 7 (FSITDR0 to FSITDR7)............................... 659
21.3.9 FSI Receive Data Register (FSIRDR) .................................................................. 659
21.3.10 FSI Access Host Base Address Registers H and L
(FSIHBARH and FSIHBARL) ............................................................................. 660
21.3.11 FSI Flash Memory Size Register (FSISR)............................................................ 661
21.3.12 FSI Command Host Base Address Registers H and L
(CMDHBARH and CMDHBARL) ...................................................................... 662
21.3.13 FSI Command Register (FSICMDR).................................................................... 662
21.3.14 FSI LPC Command Status Register 1 (FSILSTR1).............................................. 663
21.3.15 FSI LPC Command Status Register 2 (FSILSTR2).............................................. 665
21.3.16 FSI General-Purpose Registers 1 to F (FSIGPR1 to FSIGPRF) ........................... 666
21.3.17 FSI LPC Control Register (SLCR) ....................................................................... 666
21.3.18 FSI Address Registers H, M, and L (FSIARH, FSIARM, and FSIARL) ............. 667
21.3.19 FSI Write Data Registers HH, HL, LH, and LL
(FSIWDRHH, FSIWDRHL, FSIWDRLH, and FSIWDRLL).............................. 668
21.4 Operation ........................................................................................................................... 670
21.4.1 LPC/FW Memory Cycles ..................................................................................... 670
21.4.2 SPI Flash Memory Transfer.................................................................................. 672
21.4.3 Flash Memory Instructions ................................................................................... 673
21.4.4 FSI Memory Cycle (Direct Transfer between LPC and SPI)................................ 674
21.4.5 FSI Memory Cycle (LPC-SPI Command Transfer).............................................. 681
Rev. 1.00 May 09, 2008 Page xxii of xxvi