Receive Status Register (Cstr) - Renesas H8S/2100 Series Hardware Manual

Section 15 CIR Interface
15.3.3

Receive Status Register (CSTR)

CSTR indicates the data reception state of the CIR.
Bit Bit Name
7 CIRBUSY
6 CIRRDRF
5 REPF
4 OVRF
Rev. 1.00 May 09, 2008 Page 434 of 954
REJ09B0462-0100
Initial
Value R/W Description
0 R CIR Busy Flag
Indicates the data receive state of the CIR.
[Setting condition]
When the CIR starts data reception.
[Clearing condition]
When the CIR has finished data reception.
0 R Receive Data Register Full
Indicates whether CIRRDR contains a receive data
or not. This bit cannot be modified.
[Setting condition]
When a receive data is stored into CIRRDR.
[Clearing condition]
When a receive data has been read from CIRRDR.
0 R/W* Repeat Detection Flag
Indicates a repeat is generated.
[Setting condition]
When a repeat is detected.
[Clearing condition]
When writing 0 after reading REPF = 1.
0 R/W* Overrun Error Flag
Indicates CIRRDR overflows.
[Setting condition]
When the next data is stored in CIRRDR while
CIRRDR is full.
[Clearing condition]
When writing 0 after reading OVRF = 1.