Table of Contents
Advertisement
Section 28 Electrical Characteristics
Table 28.11 JTAG Timing
Conditions:
V
= 3.0 V to 3.6 V, V
CC
Item
ETCK clock cycle time
ETCK clock high pulse width
ETCK clock low pulse width
ETCK clock rise time
ETCK clock fall time
ETRST pulse width
Reset hold transition pulse width
ETMS setup time
ETMS hold time
ETDI setup time
ETDI hold time
ETDO data delay time
Note:
*
When t
cyc
ETCK
Rev. 1.00 May 09, 2008 Page 936 of 954
REJ09B0462-0100
Figure 28.24 Test Conditions for Tester
= 0 V, φ = 8 MHz to maximum operating frequency
SS
Symbol
t
TCKcyc
t
TCKH
t
TCKL
t
TCKr
t
TCKf
t
TRSTW
t
RSTHW
t
TMSS
t
TMSH
t
TDIS
t
TDIH
t
TDOD
≤ t
TCKcyc
t
TCKH
Figure 28.25 JTAG ETCK Timing
Test voltage: 0.4Vcc
50 pF
Min.
Max.
40*
125*
12
12
5
5
20
3
20
20
20
20
20
t
TCKcyc
t
TCKf
t
TCKL
Test
Unit
Conditions
ns
Figure
28.25
t
Figure
cyc
28.26
ns
Figure
28.27
t
TCKr
Advertisement
Table of Contents
