Renesas H8S/2100 Series Hardware Manual page 764

6-bit single-chip microcomputer
Hide thumbs Also See for H8S/2100 Series:
Table of Contents

Advertisement

Section 24 Flash Memory
(c)
Erasure
FPFR indicates the return value of the erasure result.
Bit
Bit Name
7
6
MD
5
EE
4
FK
Rev. 1.00 May 09, 2008 Page 738 of 954
REJ09B0462-0100
Initial
Value
R/W
R/W
R/W
R/W
Description
Unused
Returns 0.
Erasure Mode Related Setting Error Detect
Detects the error protection state and returns the result.
When the error protection state is entered, this bit is set
to 1. Whether the error protection state is entered or not
can be confirmed with the FLER bit in FCCS. For
conditions to enter the error protection state, see
section 24.9.3, Error Protection.
0: Normal operation (FLER = 0)
1: Error protection state, and programming cannot be
erased. (FLER = 1)
Erasure Execution Error Detect
Returns 1 when the user MAT could not be erased or
when the flash memory related register settings are
partially changed. If this bit is set to 1, there is a high
possibility that the user MAT has been erased partially.
In this case, after removing the error factor, erase the
user MAT. Also an attempt to erase the user MAT when
the FMATS value is H'AA and the user boot MAT is
selected leads to an erasure execution error. In that
case, both the user MAT and user boot MAT are not
erased. Erasure of the user boot MAT must be
performed in boot mode or programmer mode.
0: Erasure has ended normally.
1: Erasure has ended abnormally.
Flash Key Register Error Detect
Checks the FKEY value (H'5A) before erasure starts,
and returns the result.
0: FKEY setting is normal. (H'5A)
1: FKEY setting is abnormal. (value other than H'5A)

Advertisement

Table of Contents
loading

This manual is also suitable for:

H8s/2112r

Table of Contents