Renesas H8S/2100 Series Hardware Manual page 251

Table 10.1 TPU Functions
Item
Count clock
General registers
(TGR)
General registers/buffer
registers
I/O pins
Counter clear function
Compare 0 output
match
1 output
output
Toggle
output
Input capture function
Synchronous operation O
PWM mode
Phase counting mode
Buffer operation
Channel 0
φ/1
φ/4
φ/16
φ/64
TCLKA
TCLKB
TCLKC
TCLKD
TGRA_0
TGRB_0
TGRC_0
TGRC_0
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TGR compare match
or input capture
O
O
O
O
O

O
Section 10 16-Bit Timer Pulse Unit (TPU)
Channel 1
φ/1
φ/4
φ/16
φ/64
φ/256
TCLKA
TCLKB
TGRA_1
TGRB_1

TIOCA1
TIOCB1
TGR compare match
or input capture
O
O
O
O
O
O
O

Rev. 1.00 May 09, 2008 Page 225 of 954
Channel 2
φ/1
φ/4
φ/16
φ/64
φ/1024
TCLKA
TCLKB
TCLKC
TGRA_2
TGRB_2

TIOCA2
TIOCB2
TGR compare match or
input capture
O
O
O
O
O
O
O

REJ09B0462-0100