Renesas H8S/2100 Series Hardware Manual page 456

6-bit single-chip microcomputer

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Table of Contents

Section 15 CIR Interface

4-stage filter

SFR: Receive shift register

CCR1: Receive control register 1

CCR2: Receive control register 2

CSTR: Receive status register

CEIR: Interrupt enable register

BRR: Bit rate register

CIRRDR0 to 7: Receive data register 0 to 7

HHMIN: Header minimum high-level period register

Rev. 1.00 May 09, 2008 Page 430 of 954

REJ09B0462-0100

Module data bus

Reception control

Sampling clock

Figure 15.1 CIR Block Diagram

Baud rate generator

HHMAX: Header maximum high-level period register

HLMIN: Header minimum low-level period register

HLMAX: Header maximum low-level period register

DT1MIN: Data level 1 minimum period register

DT1MAX: Data level 1 maximum period register

DT0MIN: Data level 0 minimum period register

DT0MAX: Data level 0 maximum period register

RMIN: Repeat header minimum low-level period register

RMAX: Repeat header maximum low-level period register