Renesas H8S/2100 Series Hardware Manual page 18

14.9.4 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only) ..................................................................... 422
14.9.5 Relation between Writing to TDR and TDRE Flag .............................................. 422
14.9.6 SCI Operations during Mode Transitions ............................................................. 423
14.9.7 Notes on Switching from SCK Pins to Port Pins .................................................. 426
14.9.8 Note on Writing to Registers in Transmission, Reception,
and Simultaneous Transmission and Reception.................................................... 427
Section 15 CIR Interface ................................................................................... 429
15.1 Features.............................................................................................................................. 429
15.2 Input Pins ........................................................................................................................... 431
15.3 Register Description .......................................................................................................... 431
15.3.1 Receive Control Register 1 (CCR1) ..................................................................... 432
15.3.2 Receive Control Register 2 (CCR2) ..................................................................... 433
15.3.3 Receive Status Register (CSTR)........................................................................... 434
15.3.4 Interrupt Enable Register (CEIR) ......................................................................... 436
15.3.5 Bit Rate Register (BRR) ....................................................................................... 437
15.3.6 Receive Data Register 0 to 7 (CIRRDR0 to CIRRDR7) ...................................... 438
15.3.7 Header Minimum/Maximum High-Level Period Register
(HHMIN and HHMAX) ....................................................................................... 438
15.3.8 Header Minimum/Maximum Low-Level Period Register (HLMIN/HLMAX).... 440
15.3.9 Data Level 1 Minimum/Maximum Period Register (DT1MIN/DT1MAX) ......... 440
15.3.10 Data Level 0 Minimum/Maximum Period Register (DT0MIN/DT0MAX) ......... 441
15.3.11 Repeat Header Minimum/Maximum Low-Level Period Register
(RMIN/RMAX) .................................................................................................... 441
15.4 Operation ........................................................................................................................... 442
15.4.1 Determination of Signal Type by Low/High-Level Period................................... 444
15.4.2 Operation of FIFO Register .................................................................................. 446
15.4.3 Operation in Watch Mode..................................................................................... 447
15.4.4 Switching between System Clock and Sub Clock ................................................ 447
15.5 Noise Canceler Circuit....................................................................................................... 448
15.6 Reset Conditions ................................................................................................................ 450
15.7 Interrupt Sources................................................................................................................ 451
15.8 Usage Note......................................................................................................................... 452
Section 16 Serial Communication Interface with FIFO (SCIF)........................ 455
16.1 Features.............................................................................................................................. 455
16.2 Input/Output Pins............................................................................................................... 457
16.3 Register Descriptions ......................................................................................................... 458
16.3.1 Receive Shift Register (FRSR) ............................................................................. 459
Rev. 1.00 May 09, 2008 Page xviii of xxvi