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13.2
Input/Output Pins
The WDT has the pins listed in table 13.1.
Table 13.1 Pin Configuration
Name
External sub-clock input pin
13.3
Register Descriptions
The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have
to be written to in a method different from normal registers. For details, see section 13.6.1, Notes
on Register Access. For details on the system control register, see section 3.2.2, System Control
Register (SYSCR).
Table 13.2 Register Configuration
Channel
Register Name
Channel 0
Timer counter_0
Timer control/status
register_0
Channel 1
Timer counter_1
Timer control/status
register_1
Note:
*
Address in the upper cell: when writing.
Address in the lower cell: when reading
Pin Name
I/O
EXCL
Input
Abbreviation
R/W
TCNT_0
R/W
TCSR_0
R/W
TCNT_1
R/W
TCSR_1
R/W
Section 13 Watchdog Timer (WDT)
Function
Inputs the clock pulses to the WDT_1
prescaler counter
Initial Value
Address
H'00
H'FFA8
H'FFA9*
H'00
H'FFA8
H'FFA8*
H'00
H'FFEA
H'FFEB*
H'00
H'FFEA
H'FFEA*
Rev. 1.00 May 09, 2008 Page 351 of 954
Data Bus
Width
16
8
16
8
16
8
16
8
REJ09B0462-0100
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