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Section 11 16-Bit Cycle Measurement Timer (TCM)
(2)
Measuring a Cycle
In cycle measurement mode, one cycle of the input waveform for TCM form one measurement
cycle. Start by setting TCMMDS = 0 and then set CST = 0, which clears TCMCNT to H'0000.
After that, set an upper or lower limit on the measurement cycle in the TCMMLCM/TCMMINCM
register. Finally, place the timer in cycle measurement mode by setting the TCMMDS bit in
TCMCR to 1. TCMCNT will count cycles of the selected clock. On detection of the first edge
(either rising or falling as selected with the IEDG bit in TCMCR) of the measurement cycle,
TCMCNT is automatically cleared to H'0000. On detection of the second edge, the value in
TCMCNT is transferred to TCMICR. At this time, the value in TCMICR is compared with the
value in TCMMLCM/TCMMINCM. If TCMICR is larger than TCMMLCM, the MAXOVF bit in
TCMCSR is set to 1. If TCMICR is smaller than TCMMINCM, the MINUDF bit in TCMCSR is
set to 1. If generation of the corresponding interrupt request is enabled by the setting in TCMIER,
the request is generated. In addition, on detection of the third edge, TCMCNT is cleared to
H'0000, and the next round of measurement starts.
When the CPSPE bit in TCMCR has been cleared to 0, the next round of cycle measurement will
start, even if the MAXOVF/MINUDF flag is set to 1.
If the MAXOVF/MINUDF flag is set to 1 while the CPSPE bit in TCMCR is set to 1, counting up
by TCMCNT stops and so does cycle measurement. Subsequently clearing MAXOVF/MINUDF
to 0 automatically clears TCMCNT to H'0000, and counting up for cycle measurement is then
restarted.
Figure 11.8 shows an example of timing in speed measurement.
φ
TCMCYI
TCMCNT
clear signal
TCMCNT
input clock
TCMCNT
TCMICR
MAXOVF/
MINUDF
TCMICRF
Figure 11.8 Example of Timing in Cycle Measurement
Rev. 1.00 May 09, 2008 Page 306 of 954
REJ09B0462-0100
M
H'0000
H'0001
L
K
N - 1
M
L
N
H'0000
H'0001
N
M
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