Renesas H8S/2100 Series Hardware Manual page 570

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Section 17 I C Bus Interface (IIC)
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4. The I C bus interface specification for the SCL rise time t
speed mode). In master mode, the I
one bit at a time during communication. If t
the time determined by the input clock of the I
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in table 17.10.
Table 17.10 Permissible SCL Rise Time (t
IICX t Indication
cyc
0 7.5 t Standard mode
cyc
High-speed mode 300
1 17.5 t Standard mode
cyc
High-speed mode 300
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5. The I C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
and 300 ns. The I
table 17.11. However, because of the rise and fall times, the I
may not be satisfied at the maximum transfer rate. Table 17.11 shows output timing
calculations for different operating frequencies, including the worst-case influence of rise and
fall times.
t fails to meet the I
BUFO
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I
t in high-speed mode and t
SCLLO
specifications for worst-case calculations of t
investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and
capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices
whose input timing permits this output timing for use as slave devices connected to the I
bus.
Rev. 1.00 May 09, 2008 Page 544 of 954
REJ09B0462-0100
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C bus interface monitors the SCL line and synchronizes
2
I C Bus
Specification
(Max.)
1000
1000
2
C bus interface SCL and SDA output timing is prescribed by t
2
C bus interface specifications at any frequency. The solution is either (a)
in standard mode fail to satisfy the I
STASO
is 1000 ns or less (300 ns for high-
sr
(the time for SCL to go from low to V
sr
2
C bus interface, the high period of SCL is
) Values
sr
Time Indication [ns]
φ = φ =
8 MHz 10 MHz
937 750
← ←
← ←
← ←
2
C bus interface specifications
/t . Possible solutions that should be
Sr Sf
) exceeds
IH
φ = φ = φ =
16 MHz 20 MHz 25 MHz
468 375 300
← ← ←
←
875 700
← ← ←
, as shown in
cyc
2
C bus.
2
C bus interface
2
C