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19.4.8 Operation during Data Reception ......................................................................... 573
19.4.9 KCLK Fall Interrupt Operation ............................................................................ 574
19.4.10 First KCLK Falling Interrupt ................................................................................ 575
19.5 Usage Notes ....................................................................................................................... 579
19.5.1 KBIOE Setting and KCLK Falling Edge Detection ............................................. 579
19.5.2 KD Output by KDO bit (KBCRL) and by Automatic Transmission .................... 580
19.5.3 Module Stop Mode Setting ................................................................................... 580
19.5.4 Medium-Speed Mode ........................................................................................... 580
19.5.5 Transmit Completion Flag (KBTE) ...................................................................... 580
Section 20 LPC Interface (LPC)........................................................................581
20.1 Features.............................................................................................................................. 581
20.2 Input/Output Pins............................................................................................................... 584
20.3 Register Descriptions ......................................................................................................... 585
20.3.1 Host Interface Control Registers 0 and 1 (HICR0 and HICR1)............................ 587
20.3.2 Host Interface Control Registers 2 and 3 (HICR2 and HICR3)............................ 593
20.3.3 Host Interface Control Register 4 (HICR4) .......................................................... 596
20.3.4 Host Interface Control Register 5 (HICR5) .......................................................... 597
20.3.5 LPC Channel 1 Address Registers H and L (LADR1H and LADR1L)................ 598
20.3.6 LPC Channel 2 Address Registers H and L (LADR2H and LADR2L)................ 599
20.3.7 LPC Channel 3 Address Registers H and L (LADR3H and LADR3L)................ 601
20.3.8 LPC Channel 4 Address Registers H and L (LADR4H and LADR4L)................ 603
20.3.9 Input Data Registers 1 to 4 (IDR1 to IDR4) ......................................................... 604
20.3.10 Output Data Registers 1 to 4 (ODR1 to ODR4) ................................................... 604
20.3.11 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)..................................... 605
20.3.12 Status Registers 1 to 4 (STR1 to STR4) ............................................................... 605
20.3.13 SERIRQ Control Register 0 (SIRQCR0).............................................................. 612
20.3.14 SERIRQ Control Register 1 (SIRQCR1).............................................................. 616
20.3.15 SERIRQ Control Register 2 (SIRQCR2).............................................................. 620
20.3.16 SERIRQ Control Register 3 (SIRQCR3).............................................................. 623
20.3.17 SERIRQ Control Register 4 (SIRQCR4).............................................................. 624
20.3.18 SCIF Address Register (SCIFADRH, SCIFADRL) ............................................. 625
20.3.19 Host Interface Select Register (HISEL)................................................................ 626
20.4 Operation ........................................................................................................................... 627
20.4.1 LPC interface Activation ...................................................................................... 627
20.4.2 LPC I/O Cycles..................................................................................................... 627
20.4.3 Gate A20............................................................................................................... 630
20.4.4 LPC Interface Shutdown Function (LPCPD)........................................................ 633
20.4.5 LPC Interface Serialized Interrupt Operation (SERIRQ) ..................................... 637
20.4.6 LPC Interface Clock Start Request ....................................................................... 639
Rev. 1.00 May 09, 2008 Page xxi of xxvi
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