Table of Contents
Advertisement
22.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
1, then starts A/D conversion. Figure 22.2 shows the A/D conversion timing. Table 22.4 indicates
the A/D conversion time.
As indicated in figure 22.2, the A/D conversion time (t
(t
). The length of t
SPL
D
time therefore varies within the ranges indicated in table 22.4.
In scan mode, the values shown in table 22.4 become those for the first conversion time. The
second and subsequent conversion times are listed in table 22.5. In either case, bits CKS1 and
CKS0 in ADCR should be set so that the conversion time is within the ranges indicated by the
A/D conversion characteristics.
Address
Write signal
Input sampling
timing
ADF
varies depending on the timing of write to ADCSR. The total conversion
(1)
Pφ
(2)
t
D
[Legend]
(1):
ADCSR write cycle
(2):
ADCSR address
t
:
A/D conversion start delay time
D
t
:
Input sampling time
SPL
t
: A/D conversion time
CONV
Figure 22.2 A/D Conversion Timing
) passes after the ADST bit in ADCSR is set to
D
) includes t
CONV
t
SPL
t
CONV
Rev. 1.00 May 09, 2008 Page 703 of 954
Section 22 A/D Converter
and the input sampling time
D
REJ09B0462-0100
Advertisement
Table of Contents
