Renesas H8S/2100 Series Hardware Manual page 471

Table 15.4 An Example of Signal Type Determination Register Setting
Description
Minimum high-level period
for a header or repeat
header and minimum low-
level period for a stop
Maximum high-level period
for a header or repeat
header and maximum low-
level period for a stop
Minimum low-level period
for a header
Maximum low-level period
for a header
Minimum value of low/high-
level period for logic 0, high-
level period for logic 1, and
high-level period for a burst
Maximum value of low/high-
level period for logic 0, high-
level period for logic 1, and
high-level period for a burst
Minimum low-level period
for logic 1
Maximum low-level period
for logic 1
Minimum low-level period
for a repeat header
Maximum low-level period
for a repeat header
Note: The above table shows the values when the system clock is 10MHz, CLK1, CLK0 = B'10,
and BRR = H'82 (when the error is 30%).
Register Setting
Name Value
Symbol
HHMIN A H'079
HHMAX A H'0DF
HLMIN B H'3D
HLMAX B H'6F
DT0MIN C H'07
DT0MAX C H'0D
DT1MIN D H'0F
DT1MAX D H'1B
RMIN E H'1F
RMAX E H'37
Section 15 CIR Interface
Prescribed
Setting Time
Time (Error: 30%) Notes
6.34 ms 6.3 ms
11.7 ms 11.7 ms
3.20 ms 3.15 ms
5.82 ms 5.85 ms
0.37 ms 0.39 ms
0.68 ms 0.73 ms
0.78 ms 0.78 ms
1.42 ms 1.46 ms
1.62 ms 1.58 ms
2.88 ms 2.92 ms
Rev. 1.00 May 09, 2008 Page 445 of 954
HHMIN9 to
HHMIN0
HHMAX9 to
HHMAX0
REJ09B0462-0100