Table of Contents
Advertisement
Section 21 FSI Interface
(4)
FSI Dummy Write
Figure 21.14 shows an example of FSI dummy write.
FSI Dummy Write
FSIHBAR: H'231F
FSISR: H'00 (1 MB)
CMDHBAR: H'EFFF
H'2325_4A76
Host address
Byte-Program
H'232E_1BC3
Host address
As shown in figure 21.14, if an LPC/FW memory write cycle occurs while the FSIDMYE bit in
FSILSTR1 is 1, the FSI does not access the SPI flash memory but stores the SPI flash memory
address and write data in FSIAR and FSIWDR, respectively.
Rev. 1.00 May 09, 2008 Page 684 of 954
REJ09B0462-0100
FSIDMYE
FSIWDR[31:0]
H'73
H'0000_0073
FSIAR[23:0]
H'06_4A76
FSIDMYE
FSIWDR[31:0]
H'D4
H'0000_00D4
FSIAR[23:0]
H'0F_1BC3
Figure 21.14 FSI Dummy Write (Example)
B'1
B'0
Flash memory
H'0F_1BC3
H'D4
SPI flash memory
address
Advertisement
Table of Contents
