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8.1.1
Data Direction Register (PnDDR) (n = 1 to 6, 8, 9, A to D, and F to H)
DDR specifies the port input or output for each bit.
The upper five bits in P5DDR, the upper one bit in P8DDR, and the upper two bits in PHDDR are
reserved.
PORTS = 0
(1)
Bit
Bit Name
7
Pn7DDR
6
Pn6DDR
5
Pn5DDR
4
Pn4DDR
3
Pn3DDR
2
Pn2DDR
1
Pn1DDR
0
Pn0DDR
PORTS = 1
(2)
Bit
Bit Name
7
Pn7DDR
6
Pn6DDR
5
Pn5DDR
4
Pn4DDR
3
Pn3DDR
2
Pn2DDR
1
Pn1DDR
0
Pn0DDR
Initial Value
R/W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
The corresponding pins act as output ports when
these bits are set to 1 and act as input ports when
cleared to 0.
Note: These bits cannot be set with bit manipulation
instructions such as BSET and BCLR.
Description
The corresponding pins act as output ports when
these bits are set to 1 and act as input ports when
cleared to 0.
Rev. 1.00 May 09, 2008 Page 157 of 954
Section 8 I/O Ports
REJ09B0462-0100
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