Register Descriptions - Renesas H8S/2100 Series Hardware Manual

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3

Register Descriptions

The SCIF has the following registers. The register configuration of the SCIF is shown below.
Access to the registers is switched by the SCIFE bit in HICR5 and bit 3 in MSTPCRB. For details,
see table 16.3. For the SCIF address registers H and L (SCIFADRH, SCIFADRL) and serial IRQ
control register 4 (SIRQCR4), see section 20, LPC Interface (LPC).
Table 16.2 Register Configuration
Register Name
Host interface control register 5
Module stop control register B
Receive buffer register
Transmitter holding register
Divisor latch L
Interrupt enable register
Divisor latch H
Interrupt identification register
FIFO control register
Line control register
Modem control register
Line status register
Modem status register
Scratch pad register
SCIF control register
SCIF address register H
SCIF address register L
Serial IRQ control register 4
Rev. 1.00 May 09, 2008 Page 458 of 954
REJ09B0462-0100
Abbreviation R/W
HICR5 R/W
MSTPCRB R/W
FRBR R
FTHR W
FDLL R/W
FIER R/W
FDLH R/W
FIIR R
FFCR W
FLCR R/W
FMCR R/W
FLSR R
FMSR R
FSCR R/W
SCIFCR R/W
SCIFADRH R/W
SCIFADRL R/W
SIRQCR4 R/W
Initial Value Address
H'00 H'FFFE33
H'00 H'FFFE7F
H'00 H'FFFC20

H'00
H'00 H'FFFC21
H'00
H'01 H'FFFC22
H'00
H'00 H'FFFC23
H'00 H'FFFC24
H'60 H'FFFC25

H'FFFC26
H'00 H'FFFC27
H'00 H'FFFC28
H'03 H'FFFDC4
H'F8 H'FFFDC5
H'00 H'FFFE3B
Data
Bus
Width
8
8
8
8
8
8
8
8
8
8
8
8
8
8