Renesas H8S/2100 Series Hardware Manual page 241

6-bit single-chip microcomputer

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Figure 9.3 Block Diagram of 12 and 16-bit Single Pulse Mode

When the PWMnE bit (n = 0 to 5) in PWMOUTCR is set to 1, the PWMU outputs pulses that start

with a high level. The updated PWMREG value is written in REGLAT, and the updated

PWMPRE value is written in PRELAT.

When the REGLAT value is less than the duty counter value, the PWMU outputs a high level

(when direct output is selected). At each PWM clock timing, the duty counter is incremented.

When the clock generator counter is H'00, the PWM clock is generated by decrementing the

PRELAT value.

Figure 9.4 shows an example of duty counter and clock generator counter operation.

Clock generator

Figure 9.4 Example of Duty Counter and Clock Generator Counter Operation

(When PWMPRE = H'01 and PWMREG = H'80 with φ/4 Selected as Count Clock Source)

Section 9 8-Bit PWM Timer (PWMU)

Comparator 0

Comparator 1

Rev. 1.00 May 09, 2008 Page 215 of 954

(Output disabled)

REJ09B0462-0100