Register Descriptions - Renesas H8S/2100 Series Hardware Manual

17.3

Register Descriptions

2
The I C bus interface has the following registers. Registers ICDR and SARX and registers ICMR
and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit
in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit
is set to 1, ICMR and ICDR can be accessed. For details on the serial timer control register, see
section 3.2.3, Serial Timer Control Register (STCR).
Table 17.2 Register Configuration
Channel Register Name
2
Channel 0 I C bus extended control register_0
2
I C bus control register_0
2
I C bus status register_0
2
I C bus data register_0
Second slave address register_0
2
I C bus mode register_0
Slave address register_0
2
I C bus control initialization
register_0
2
Channel 2 I C bus extended control register_2
2
I C bus control register_2
2
I C bus status register_2
2
I C bus data register_2
Second slave address register_2
2
I C bus mode register_2
Slave address register_2
2
I C bus control initialization
register_2
Section 17 I
Abbreviation R/W
ICXR_0 R/W H'00
ICCR_0 R/W H'01
ICSR_0 R/W H'00
R/W 
ICDR_0
SARX_0 R/W H'01
ICMR_0 R/W H'00
SAR_0 R/W H'00
ICRES_0 R/W H'0F
ICXR_2 R/W H'00
ICCR_2 R/W H'01
ICSR_2 R/W H'00
R/W 
ICDR_2
SARX_2 R/W H'01
ICMR_2 R/W H'00
SAR_2 R/W H'00
ICRES_2 R/W H'0F
Rev. 1.00 May 09, 2008 Page 495 of 954
2
C Bus Interface (IIC)
Initial Data Bus
Value Address Width
H'FED4 8
H'FFD8 8
H'FFD9 8
H'FFDE 8
H'FFDE 8
H'FFDF 8
H'FFDF 8
H'FEE6 8
H'FE8C 8
H'FE88 8
H'FE89 8
H'FE8E 8
H'FE8E 8
H'FE8F 8
H'FE8F 8
H'FE8A 8
REJ09B0462-0100