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(3)
P84/IRQ3/TxD1
The pin function is switched as shown below according to the combination of the TE bit in SCR of
SCI_1 and the P84DDR bit. When the ISS3 bit in ISSR is cleared to 0 and the IRQ3E bit in IER of
the interrupt controller is set to 1, this pin functions as the IRQ3 input pin.
TE
P84DDR
Pin function
(4)
P83/LPCPD
The pin function is switched as shown below according to the combination of the FSILIE bit in
SLCR of FSI, and the SCIFE bit in HICR5, the LPC4E bit in HICR4, and the LPC3E to LPC1E
bits in HICR0 of LPC, and the P83DDR bit. LPCENABLE in the following table is expressed by
the following logical expression.
LPCENABLE = 1: FSILIE + SCIFE + LPC4E + LPC3E + LPC2E + LPC1E
LPCENABLE
P83DDR
Pin function
(5)
P82/CLKRUN
The pin function is switched as shown below according to the combination of the FSILIE bit in
SLCR of FSI, and the SCIFE bit in HICR5, the LPC4E bit in HICR4, and the LPC3E to LPC1E
bits in HICR0 of LPC, and the P82DDR bit. LPCENABLE in the following table is expressed by
the following logical expression.
LPCENABLE = 1: FSILIE + SCIFE + LPC4E + LPC3E + LPC2E + LPC1E
LPCENABLE
P82DDR
Pin function
0
0
P84 input pin
0
0
P83 input pin
0
0
P82 input pin
1
P84 output pin
IRQ3 input pin
1
P83 output pin
1
P82 output pin
Rev. 1.00 May 09, 2008 Page 173 of 954
Section 8 I/O Ports
1
TxD1 output pin
1
LPCPD input pin
1
CLKRUN I/O pin
REJ09B0462-0100
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