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Section 9 8-Bit PWM Timer (PWMU)
9.3.6
PWM Duty Setting Latch Register (REGLAT)
REGLAT is a shift register in PWMREG. When one pulse is completed, the data of PWMREG is
transferred to PRELAT automatically. This register cannot be accessed by the CPU directly.
Table 9.3
Counter Operation of the Channel 0 and 1
CNTMD01A in
CNTMD01B in
PWMMDCR
PWMMDCR
0
0
0
1
1
0
1
1
Note:
When 12/16-bit counter is selected, single pulse mode must be selected.
Table 9.4
Counter Operation of the Channel 2 and 3
CNTMD23A in
CNTMD23B in
PWMMPCR
PWMOUTCR
0
0
0
1
1
0
1
1
Note:
When 12/16-bit counter is selected, single pulse mode must be selected.
Rev. 1.00 May 09, 2008 Page 208 of 954
REJ09B0462-0100
Counter Operation of the Channel 0 and 1
8-bit counter operation
12-bit counter operation
(higher order: channel 1, lower order: channel 0)
16-bit counter operation
(higher order: channel 1, lower order: channel 0)
Setting prohibited
Counter Operation of the Channel 2 and 3
8-bit counter operation
12-bit counter operation
(higher order: channel 3, lower order: channel 2)
16-bit counter operation
(higher order: channel 3, lower order: channel 2)
Setting prohibited
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