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• STR2
Bit
Bit Name Initial Value Slave Host Description
7
DBU27
0
6
DBU26
0
5
DBU25
0
4
DBU24
0
3
C/D2
0
2
DBU22
0
1
IBF2
0
0
OBF2
0
Note:
Only 0 can be written to clear the flag.
*
R/W
R/W
R
Defined by User
R/W
R
The user can use these bits as necessary.
R/W
R
R/W
R
R
R
Command/Data
When the host writes to IDR2, bit 2 of the I/O
address is written into this bit to indicate whether
IDR2 contains data or a command.
0: Content of input data register (IDR2) is a data
1: Content of input data register (IDR2) is a
command
R/W
R
Defined by User
The user can use this bit as necessary.
R
R
Input Buffer Full
This bit is an internal interrupt source to the slave
(this LSI).
0: [Clearing condition]
When the slave reads IDR2
1: [Setting condition]
When the host writes to IDR2 in I/O write cycle
R/(W)* R
Output Buffer Full
0: [Clearing conditions]
•
When the host reads ODR2 in I/O read cycle
•
When the slave writes 0 to the OBF2 bit
1: [Setting condition]
When the slave writes to ODR2
Section 20 LPC Interface (LPC)
Rev. 1.00 May 09, 2008 Page 607 of 954
REJ09B0462-0100
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