Renesas H8S/2100 Series Hardware Manual page 662

6-bit single-chip microcomputer
Hide thumbs Also See for H8S/2100 Series:
Table of Contents

Advertisement

Section 20 LPC Interface (LPC)
Figure 20.5 shows the timing of the LPCPD and LRESET signals.
LCLK
LPCPD
LAD3 to LAD0
LFRAME
LRESET
Rev. 1.00 May 09, 2008 Page 636 of 954
REJ09B0462-0100
At least 30 µs
Figure 20.5 Power-Down State Termination Timing
At least 100 µs
At least 60 µs

Advertisement

Table of Contents
loading

This manual is also suitable for:

H8s/2112r

Table of Contents