Renesas H8S/2100 Series Hardware Manual page 717

Register Name
FSICR1 Bits 7 to 0
FSICR2 Bits 7 and 6
Bits 5 to 0
FSIBNR Bits 7 to 4
Bit 3
Bits 2 to 0
FSIINS Bits 7 to 0
FSIRDINS Bits 7 to 0
FSIPPINS Bits 7 to 0
FSISTR Bit 7
Bits 6 and 5
Bits 4 to 0
FSITDR7 to Bits 7 to 0
FSITDR0
FSIRDR Bits 7 to 0
FSI internal sequencer
System
Reset LPC Reset
Initialized Retained
Initialized Retained
Initialized Retained
Initialized Retained
Initialized Retained
Initialized Retained
Initialized Retained
Initialized Retained
Initialized Retained
Initialized Retained
Initialized Initialized
Initialized Retained
Initialized Retained
Initialized Retained
Initialized Retained
Section 21 FSI Interface
LPC
Shutdown LPC Abort
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Rev. 1.00 May 09, 2008 Page 691 of 954
FSI Reset
Retained
Initialized
Retained
Initialized
Retained
Initialized
Retained
Retained
Retained
Initialized
Initialized
Retained
Retained
Retained
Initialized
REJ09B0462-0100