Receive Control Register 1 (Ccr1) - Renesas H8S/2100 Series Hardware Manual

Section 15 CIR Interface
Register Name
Repeat header minimum low-level period
register
Repeat header maximum low-level period
register
Notes: 1. Before accessing these registers, clear the MSTPA3 bit (bit 3) in MSTPCRA to 0.
2. See the description of each register for details on R/W.
15.3.1

Receive Control Register 1 (CCR1)

CCR1 enable/disable the CIR reception, controls a software reset of the CIR, select the polarity of
the CIR input signals, and select the reference clock for CIR reception.
Bit Bit Name
7 CIRE
6 SRES
5 CPHS
4 MLS
Rev. 1.00 May 09, 2008 Page 432 of 954
REJ09B0462-0100
Abbreviation
RMIN
RMAX
Initial
Value R/W Description
0 R/W CIR Receive Enable
0: The CIR reception is disabled.
1: The CIR reception is enabled (Port is CIRI input
pin).
0 R/W CIR Software Reset
Controls initialization of the internal sequencer of the
CIR.
0: Normal operation
1: The internal sequencer is cleared.
Writing 1 to this bit generates a clear signal for the
internal sequencer in the corresponding module,
resulting in the initialization of the CIR's internal state.
0 R/W Input Signal Polarity Select
0: CIR input signal is used as is.
1: CIR input signal is inverted before use.
0 R/W Receive Data Format Select
0: LSB-first data is received.
1: MSB-first data is received.
R/W Initial Value
R/W H'00
R/W H'00
Address
H'FA50
H'FA51