Renesas H8S/2100 Series Hardware Manual page 349

Table 12.3 Clock Input to TCNT and Count Condition (1)
Channel CKS2 CKS1
TMR_0 0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
TMR_1 0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
TCR
CKS0 ICKS1
0 —
1 —
1 —
0 —
0 —
1 —
1 —
0 —
0 —
1 0
1 1
0 0
0 1
1 0
1 1
0 —
STCR
ICKS0 Description
— Disables clock input
0 Increments at falling edge of internal
clock φ/8
1 Increments at falling edge of internal
clock φ/2
0 Increments at falling edge of internal
clock φ/64
1 Increments at falling edge of internal
clock φ/32
0 Increments at falling edge of internal
clock φ/1024
1 Increments at falling edge of internal
clock φ/256
— Increments at overflow signal from
TCNT_1*
— Disables clock input
— Increments at falling edge of internal
clock φ/8
— Increments at falling edge of internal
clock φ/2
— Increments at falling edge of internal
clock φ/64
— Increments at falling edge of internal
clock φ/128
— Increments at falling edge of internal
clock φ/1024
— Increments at falling edge of internal
clock φ/2048
— Increments at compare-match A from
TCNT_0*
Rev. 1.00 May 09, 2008 Page 323 of 954
Section 12 8-Bit Timer (TMR)
REJ09B0462-0100