Renesas H8S/2100 Series Hardware Manual page 514

Section 16 Serial Communication Interface with FIFO (SCIF)
Table 16.8 shows the range of initialization of the registers related to data transmission/reception
through the LPC interface, making a classification by each mode.
Table 16.8 Register States
Register
SCIFADRH Bits 15 to 8
SCIFADRL Bits 7 to 0
HICR5 SCIFE
SIRQCR4 Bits 7 to 4,
SCSIRQ3 to 0
SCIFCR SCIFOE1,
SCIFOE0,
OUT2LOOP,
CKSEL1,
CKSEL0,
SCIFRST,
REGRST
FRBR Bits 7 to 0
FTHR Bits 7 to 0
FDLL Bits 7 to 0
FDLH Bits 7 to 0
FIIR FIFOE1,
FIFOE0,
INTID2 to
INTID0,
INTPEND
FFCR RCVRTRIG1,
RCVRTRIG0,
XMITFRST,
RCVRFRST,
FIFOE
FLCR DLAB, BREAK,
EPS, PEN,
STOP, CLS1,
CLS0
Rev. 1.00 May 09, 2008 Page 488 of 954
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System
Reset SCIFRST REGRST
Initialized Stopped
Initialized Stopped
Initialized Stopped
Initialized Stopped
Initialized Stopped
Initialized Stopped
Initialized Stopped
Initialized Stopped
Initialized Stopped
Initialized Stopped
Initialized Stopped
Initialized Stopped
LPC
Reset
Stopped Stopped Stopped
Stopped Stopped Stopped
Stopped Stopped Stopped
Stopped Stopped Stopped
Stopped Stopped Stopped
Initialized Initialized Stopped
Initialized Initialized Stopped
Initialized Initialized Stopped
Initialized Initialized Stopped
Initialized Initialized Stopped
Initialized Initialized Stopped
Initialized Initialized Stopped
LPC LPC
Shutdown Abort
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped
Stopped