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Section 21 FSI Interface
Bit
Bit Name
6
OBF
5
FSIRXI
4 to 0
Note:
*
Only 0 can be written to bit 7 to clear it.
Rev. 1.00 May 09, 2008 Page 658 of 954
REJ09B0462-0100
R/W
Initial
Value
EC
Host Description
0
R
0
R
All 0
R/W
Transmit Data Register Full
Indicates whether or not there is data to be written by
the EC (this LSI).
0: There is no write data.
[Clearing condition]
When write data transmission to the SPI flash
memory is completed.
1: There is write data.
[Setting condition]
When the TE bit is set to 1.
FSI Receive End Interrupt Flag
Indicates whether or not there is data to be read by
the EC (this LSI).
0: There is no read data.
[Clearing condition]
•
LFBUSY = 0: When all receive data has been
read by the EC (when RBN is cleared to 0).
•
LFBUSY = 1: When all receive data has been I/O-
read by the host (automatically cleared).
1: There is read data.
[Setting condition]
When receive data has been transferred to FSIRDR.
Reserved
The initial value should not be modified.
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