Renesas H8S/2100 Series Hardware Manual page 273

Bit Bit Name
3 TGFD
2 TGFC
Initial
value R/W Description
0 R/(W)* Input Capture/Output Compare Flag D
Status flag that indicates the occurrence of TGRD input
capture or compare match in channel 0.
In channels 1 and 2, bit 3 is reserved. It is always read
as 0 and cannot be modified.
[Setting conditions]
•
•
[Clearing condition]
When 0 is written to TGFD after reading TGFD = 1
0 R/(W)* Input Capture/Output Compare Flag C
Status flag that indicates the occurrence of TGRC input
capture or compare match in channel 0.
In channels 1 and 2, bit 2 is reserved. It is always read
as 0 and cannot be modified.
[Setting conditions]
•
•
[Clearing condition]
When 0 is written to TGFC after reading TGFC = 1
Section 10 16-Bit Timer Pulse Unit (TPU)
When TCNT = TGRD while TGRD is functioning as
output compare register
When TCNT value is transferred to TGRD by input
capture signal while TGRD is functioning as input
capture register
When the TCNT = TGRC while TGRC is functioning
as output compare register
When TCNT value is transferred to TGRC by input
capture signal while TGRC is functioning as input
capture register
Rev. 1.00 May 09, 2008 Page 247 of 954
REJ09B0462-0100