Index - Renesas H8S/2100 Series Hardware Manual

Numerics
16-bit count mode................................... 339
16-bit cycle measurement timer (TCM) . 291
16-bit timer pulse unit............................. 223
8-bit timer (TMR) ................................... 315
A
A/D converter ......................................... 693
A/D converter activation......................... 275
Absolute address....................................... 55
Address map ............................................. 73
Address space ........................................... 33
Addressing modes..................................... 54
ADI ......................................................... 704
Arithmetic operations instructions............ 45
Asynchronous mode ............................... 383
B
Bcc...................................................... 42, 50
Bit manipulation instructions.................... 48
Bit rate .................................................... 377
Block data transfer instructions ................ 52
Block structure........................................ 720
Boot mode ...................................... 717, 743
Branch instructions ................................... 50
Buffer operation...................................... 261
Bus controller (BSC) .............................. 147
C
Cascaded connection .............................. 339
Clock pulse generator ............................. 801
Clocked synchronous mode .................... 400
CMIA...................................................... 343
CMIB...................................................... 343

Index

Communications protocol ....................... 772
Compare-match count mode ................... 339
Condition field .......................................... 53
Condition-code register (CCR) ................. 37
Conversion time ...................................... 703
CPU operating modes ............................... 31
Crystal resonator ..................................... 802
Cycle measurement mode ....................... 305
D
Data transfer instructions .......................... 44
Download pass/fail result parameter....... 734
E
Effective address................................. 54, 58
Effective address extension....................... 53
ERI1........................................................ 420
Error protection....................................... 767
Exception handling ................................... 87
Exception handling vector table.......... 88, 90
Extended control register (EXR)............... 36
Extended vector mode............................. 121
External clock ......................................... 803
F
Flash erase block select parameter.......... 742
Flash memory ......................................... 715
Flash multipurpose address area
parameter ................................................ 741
Flash multipurpose data destination
parameter ................................................ 741
Flash pass and fail parameter .................. 735
Flash program/erase frequency
parameter ................................................ 740
Rev. 1.00 May 09, 2008 Page 949 of 954
REJ09B0462-0100