Section 21 FSI Interface
21.6
Interrupt Sources
The FSI has four interrupt sources for the slave (this LSI): FSITEI, FSIRXI, FSICMDI, and
FSIWI. FSITEI is a transmit end interrupt when the slave executes the SPI flash memory write
transfer. FSIRXI is a receive end interrupt when the slave executes the SPI flash memory read
transfer. FSICMDI is a command receive interrupt in host FSI command write. FSIWI is a write
receive interrupt in the case of write from the host to the SPI flash memory. Setting the
corresponding enable bit to 1 enables the relevant interrupt request to be issued.
Table 21.9 FSI Interrupt Sources
Interrupt Name
FSII
FSITEI
FSIRXI
LFSII
FSICMDI
FSIWI
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Interrupt Source
Transmit end
Receive data full
FSI command reception
FSI write reception
Interrupt Enable Bit
FSITEIE
FSIRXIE
FSICMDIE
FSIWIE