Operation; Pulse Output - Renesas H8S/2100 Series Hardware Manual

6-bit single-chip microcomputer

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Section 12 8-Bit Timer (TMR)

Operation

Figure 12.3 shows an example for outputting an arbitrary duty pulse.

1. Clear the CCLR1 bit in TCR to 0, and set the CCLR0 bit in TCR to 1 so that TCNT is cleared

according to the compare match of TCORA.

2. Set the OS3 to OS0 bits in TCSR to B'0110 so that 1 is output according to the compare match

of TCORA and 0 is output according to the compare match of TCORB.

According to the above settings, the waveforms with the TCORA cycle and TCORB pulse width

can be output without the intervention of software.

Rev. 1.00 May 09, 2008 Page 334 of 954

REJ09B0462-0100

Figure 12.3 Pulse Output Example

Counter clear