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Section 6 Interrupt Controller
A block diagram of interrupts IRQ15 to IRQ0 is shown in figure 6.4.
IRQn
ISSm
ExIRQn
n = 15 to 7
m = 15 to 7
Note: Switching between the IRQ6 and ExIRQ6 pins is controlled by the EIVS bit.
Figure 6.4 Block Diagram of Interrupts IRQ15 to IRQ0
(3)
KIN15 to KIN0 Interrupts
Interrupts KIN15 to KIN0 are requested by the input signals on pins KIN15 to KIN0. Functions of
interrupts KIN15 to KIN0 change as follows according to the setting of the EIVS bit in system
control register 3 (SYSCR3).
• H8S/2140B Group compatible vector mode (EIVS = 0 in SYSCR3)
Interrupts KIN15 to KIN8 correspond to interrupt IRQ7, and interrupts KIN7 to KIN0
correspond to interrupt IRQ6. The pin conditions for generating an interrupt request,
whether the interrupt request is enabled, interrupt control level setting, and status of the
interrupt request for the above interrupts are in accordance with the settings and status of
the relevant interrupts IRQ7 and IRQ6.
KIN15 to KIN0 interrupt requests can be masked by using KMIMRA and KMIMRB.
If the KIN7 to KIN0 pins are specified to be used as key-sensing interrupt input pins, the
interrupt sensing condition for the corresponding interrupt source (IRQ6 or IRQ7) must be
set to low-level sensing or falling-edge sensing.
When using the IRQ6 pin as the IRQ6 interrupt input pin, the KMIMR6 bit must be cleared
to 0. When using the IRQ7 pin as the IRQ7 interrupt input pin, the KMIMR15 to KMIMR8
bits must all be set to 1. If even one of these bits is cleared to 0, the IRQ7 interrupt input
from the IRQ7 pin is ignored.
Rev. 1.00 May 09, 2008 Page 120 of 954
REJ09B0462-0100
IRQnSCA, IRQnSCB
Edge/level
detection circuit
Clear signal
IRQnE
IRQnF
S
Q
R
IRQn interrupt
request
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