Register Descriptions; A/D Data Registers A To H (Addra To Addrh) - Renesas H8S/2100 Series Hardware Manual

Section 22 A/D Converter
22.3

Register Descriptions

The A/D converter has the following registers.
Table 22.2 Register Configuration
Register Name
A/D data register A
A/D data register B
A/D data register C
A/D data register D
A/D data register E
A/D data register F
A/D data register G
A/D data register H
A/D control/status register
A/D control register
22.3.1

A/D Data Registers A to H (ADDRA to ADDRH)

There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of
A/D conversion. The ADDR registers which store a conversion result for each channel are shown
in table 22.3.
The 10-bit conversion data is stored in bits 15 to 6. The lower six bits are always read as 0.
The data bus between the CPU and the A/D converter is sixteen bits wide. The data can be read
directly from the CPU. ADDR must not be accessed in 8-bit units and must be accessed in 16-bit
units.
Rev. 1.00 May 09, 2008 Page 696 of 954
REJ09B0462-0100
Abbreviation R/W
ADDRA R
ADDRB R
ADDRC R
ADDRD R
ADDRE R
ADDRF R
ADDRG R
ADDRH R
ADCSR R/W
ADCR R/W
Initial Value Address
H'0000 H'FC00
H'0000 H'FC02
H'0000 H'FC04
H'0000 H'FC06
H'0000 H'FC08
H'0000 H'FC0A
H'0000 H'FC0C
H'0000 H'FC0E
H'00 H'FC10
H'00 H'FC11
Data Bus
Width
16
16
16
16
16
16
16
16
8
8