Operation In Asynchronous Communication - Renesas H8S/2100 Series Hardware Manual

6-bit single-chip microcomputer

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Operation in Asynchronous Communication

Figure 16.2 illustrates the typical format for asynchronous serial communication. One frame

consists of a start bit (low level), followed by transmit/receive data (LSB-first: from the least

significant bit), a parity bit, and a stop bit (high level). In asynchronous serial communication, the

transmission line is usually held high in the mark state (high level). The SCIF monitors the

transmission line, and when it detects the space state (low level), recognizes a start bit and starts

serial communication. Inside the SCIF, the transmitter and receiver are independent units,

enabling full-duplex communication. Both of the transmitter and receiver also have a 16-stage

FIFO buffered structure so that data can be read or written during transmission or reception,

enabling continuous data transmission and reception.

Figure 16.2 Data Format in Serial Transmission/Reception

Transmit/receive data

5, 6, 7, or 8 bits

One unit of transfer data (character or frame)

(Example with 8-Bit Data, Parity and 2 Stop Bits)

Section 16 Serial Communication Interface with FIFO (SCIF)

Rev. 1.00 May 09, 2008 Page 477 of 954

Idle state (mark state)

REJ09B0462-0100