Table of Contents
Advertisement
(3)
16-Bit Single Pulse Mode
Directly set the high period of the pulse for PWM output. With cascade-connected PWMREG
registers, the duty cycle of the PWM output pulse is specified as a value from 0/65535 to
65535/65535.
When the PWMREG value is m, the high period of the output pulse is calculated as follows:
Output pulse high period = (PWM cycle × m) / 65535 (0 ≤ m ≤ 65535)
Set the respective high-level pulse periods by using the following register combinations (cascaded
connection): PWMREG1 (higher order) and PWMREG0 (lower order), PWMREG3 (higher order)
and PWMREG2 (lower order), and PWMREG5 (higher order) and PWMREG4 (lower order).
Note: The higher order registers must be set after setting the lower order registers, otherwise the
output performance is not as desired.
(4)
8-Bit Pulse Division Mode
Specify the basic pulse duty cycle and the number of additional pulses for PWM output. The
higher-order four bits of the PWMREG setting specify the duty cycle of the basic pulse as 0/16 to
15/16 with a resolution of 1/16, and the lower-order four bits specify the number of pulses to be
added within the conversion period comprising the basic pulses.
Section 9 8-Bit PWM Timer (PWMU)
Rev. 1.00 May 09, 2008 Page 213 of 954
REJ09B0462-0100
Advertisement
Table of Contents
