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After the VCC is turned on with the RES pin held low, namely in the state of pin reset, if the RES
pin is driven high in the state that the VCC stays higher than the level of Vpor, the power-on reset
function is disabled and a reset exception handling starts before entering the power-on reset time.
In this case, the PORF bit is cleared to 0. When the VCC is below the level of Vpor and the RES
pin is driven high, the power-on reset is enabled. In this case, when the VCC reaches or exceeds
the level of Vpor and stays at the level after the elapse of the power-on reset time, the power-on
reset is canceled and a reset exception handling starts. At this time, the PORF bit is set to 1.
4.6
Watchdog Timer Reset
This is an internal reset generated by the watchdog timer.
When the RST/NMI bit in TCSR is set to 1, if the TCNT overflows, a watchdog timer reset is
issued for 518 system clocks.
For details of the watchdog timer reset, see section 13, Watchdog Timer (WDT).
4.7
Determination of Reset Generation Source
Reading RSTSR and SYSCR determines which reset generation source was used to execute the
reset exception handling. Figure 4.3 shows an example the flow to identify a reset generation
source.
Yes
Watchdog timer reset
Figure 4.3 Example of Reset Generation Source Determination Flow
Reset
exception handling
No
SYSCR.
XRST = 0
No
RSTSR.
PORF=1
Yes
Power-on reset
Rev. 1.00 May 09, 2008 Page 85 of 954
Section 4 Resets
Pin reset
REJ09B0462-0100
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