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Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.7
Interrupt Identification Register (FIIR)
FIIR consists of bits that identify interrupt sources. For details, see table 16.4.
Bit
Bit Name
7
FIFOE1
6
FIFOE0
5, 4
3
INTID2
2
INTID1
1
INTID0
0
INTPEND
Rev. 1.00 May 09, 2008 Page 462 of 954
REJ09B0462-0100
Initial Value
R/W
0
R
0
R
All 0
R
0
R
0
R
0
R
1
R
Description
FIFO Enable 1, 0
These bits indicate the transmit/receive FIFO
setting.
00: Transmit/receive FIFOs disabled
11: Transmit/receive FIFOs enabled
Reserved
These bits are always read as 0 and cannot be
modified.
Interrupt ID2, ID1, ID0
These bits Indicate the interrupt of the highest
priority among the pending interrupts.
000: Modem status
001: FTHR empty
010: Receive data ready
011: Receive line status
110: Character timeout (when the FIFO is enabled)
Interrupt Pending
Indicates whether one or more interrupts are
pending.
0: Interrupt pending
1: No interrupt pending
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