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Section 15 CIR Interface
15.5
Noise Canceler Circuit
The CIR incorporates a 4-stage noise canceler. The FLTE, FLT, and FLTCK1 and FLTCK0 bits
in HHMAX enable/disable the noise canceler circuit, select the number of stages of the noise
canceler circuit, and select the division ratio for generating the noise canceler circuit clock,
respectively. Figure 15.6 shows a block diagram of the noise canceler circuit.
CIRI
F. F
F. F
φ
φ/2
φ/4
φ
SUB
Rev. 1.00 May 09, 2008 Page 448 of 954
REJ09B0462-0100
FLTE = 0
F. F
F. F
F. F
F. F
F. F
FLTCK1, FLTCK0
Sampling clock generation circuit
Figure 15.8 Noise Canceler Circuit
Noise canceler circuit
Clock generation circuit for noise canceler circuit
CIR DATA
F. F
CIR sampling clock
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