Renesas H8S/2100 Series Hardware Manual page 709

6-bit single-chip microcomputer

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FSI Command Read

Figure 21.13 shows an example of FSI command read.

CMDHBAR: H'EFFF

Note: The upper 16 bits of the host address are set to the value in the CMDHBAR register.

As shown in figure 21.13, if a host address ranging from H'EFFF_F000 to H'EFFF_F00F is

accessed in LPC/FW memory read cycle while the CMDHBAR register is set to H'EFFF, the

FSILSTR1 or data in FSIGPR1 to FSIGPRF is returned. Sync is not returned if the host address to

be input is out of the determined range. In FSI command read, no wait cycle will be inserted to the

LPC bus cycle. Before reading the FSIGPR, ensure that the CMDBUSY bit in FSILSTR1 has

been cleared to 0.

Host address

Figure 21.13 FSI Command Read (Example)

FSIGPR2 to D

Rev. 1.00 May 09, 2008 Page 683 of 954

Section 21 FSI Interface

LPC internal flags

EC CPU write

REJ09B0462-0100