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SCL
8
9
(master output)
SDA
Bit 0
(master output)
Data 1
[7]
SDA
A
(slave output)
ICDRE
IRIC
IRTR
ICDR
Data 1
User processing
[9] ICDR write
Figure 17.9 Example of Stop Condition Issuance Operation Timing
1
2
3
4
Bit 7
Bit 6
Bit 5
Bit 4
[9] IRIC clear
in Master Transmit Mode (MLS = WAIT = 0)
5
6
7
8
Bit 3
Bit 2
Bit 1
Bit 0
Data 2
Data 2
[11] ACKB read
Rev. 1.00 May 09, 2008 Page 527 of 954
2
Section 17 I
C Bus Interface (IIC)
Stop condition issuance
9
[10]
A
[12] Set BBSY= 0 and
SCP= 0
(Stop condition issuance)
[12] IRIC clear
REJ09B0462-0100
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