Renesas H8S/2100 Series Hardware Manual page 518

2
Section 17 I C Bus Interface (IIC)
• Direct bus drive (SCL/SDA pin)
 Ten pins—P52/SCL0, P97/SDA0, PG0/SDAA, PG 1/SCLA, PG2/SDAB, PG3/SCLB,
PG4/SDAC, PG5/SCLC, PG6/SDAD, and PG7/SCLD —(normally NMOS push-pull
outputs) function as NMOS open-drain outputs when the bus drive function is selected.
Note: When using this IIC module, make sure to set bits HNDS, FNC1, and FNC0 in ICXR to 1
in the initial settings. If other settings are made, restrictions on operation that are not
covered in this manual will apply.
Figure 17.1 shows a block diagram of the I
pin connections to external circuits. Since I
normal port pins, they have different specifications for permissible applied voltages. For details,
see section 28, Electrical Characteristics.
φ
SCL
*
SCLA
*
SCLB
*
SCLC
*
SCLD
SDA
*
SDAA
*
SDAB
*
SDAC
*
SDAD
[Legend]
2
ICCR: I C bus control register
2
ICMR: I C bus mode register
2
ICSR: I C bus status register
2
ICDR: I C bus data register
2
ICXR: I C bus extended control register
SAR: Slave address register
SARX: Slave address register X
PS: Prescaler
Note : * An input/output pin can be selected among four pins (IIC_2).
Rev. 1.00 May 09, 2008 Page 492 of 954
REJ09B0462-0100
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2
PS
Clock
control
Noise
canceler
Bus state
decision
circuit
Arbitration
decision
circuit
Output data
control
circuit
Noise
canceler
Figure 17.1 Block Diagram of I
C bus interface. Figure 17.2 shows an example of I/O
C bus interface I/O pins are different in structure from
Address
comparator
SAR, SARX
generator
2
C Bus Interface
ICXR
ICCR
ICMR
ICSR
ICDRT
ICDRS
ICDRR
Interrupt
Interrupt
request