Renesas H8S/2100 Series Hardware Manual page 703

6-bit single-chip microcomputer

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AAI-Program Instruction

If an LPC/FW memory write cycle occurs while the AAIE bit in FSICR1 is set to 1 and the

FSIDMYE bit in FSILSTR1 is cleared to 0, and the FLDCT bit in SLCR and the FLWAIT bit in

SLCR are set to 1, the flash memory address and write data are stored in FSIAR and FSIWDR,

respectively. Then, the flash memory address, write data, and the AAI-Program instruction which

is stored in FSI hardware in advance are transferred to FSITDR. After SYNC (long wait) has been

returned, the transmit enable signal TE is set, and AAI-Program instruction execution starts. In the

first byte, the instruction, address, and data in this order are transmitted to the SPI flash memory.

In the second and the following bytes, an instruction and data in this order are transmitted to the

SPI flash memory. When the transmission has been completed, SYNC (Ready) and TAR are

returned to the host. To execute the AAI-Program instruction, byte transfer access in LPC memory

write cycle or FW memory write cycle should be performed. To return to the AAI-Program

instruction (first byte), clear the AAIE bit once or perform initialization of the FSI internal

sequencer in SRES of FSICR1. After the Read instruction or the LPC-SPI command is transferred

during the AAI-Program instruction execution, the FSI internal sequencer is initialized to return to

the AAI-Program Instruction (first byte). Figures 21.6 and 21.7 show AAI-Program execution

FSIWDR[31:0]

FSICR2 TE bit

FSISTR OBF bit

FSICK (CPOS = CPHS = 0)

Figure 21.6 AAI-Program Instruction Execution Timing (First Byte)

H'01-70-4A-06-AF

H'AF->06->4A->70->01

Rev. 1.00 May 09, 2008 Page 677 of 954

Section 21 FSI Interface

REJ09B0462-0100