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Section 4 Resets
4.5
Power-on Reset
This is an internal reset generated by the power-on reset. A power-on with the RES pin held high
generates the power-on reset. When VCC exceeds the level of Vpor, the power-on reset is
canceled after the elapse of the specified time (the power-on reset time). The power-on reset time
is the stabilization time for the external power supply and LSI. When the power supply voltage
falls down with RES pin held high and the VCC goes below the level of Vpor, a power-on reset is
generated. Then when the VCC rises to exceed the level of Vpor, the power-on reset is canceled
after the elapse of the power-on reset time. If a power-on reset is generated, the PORF bit in
RSTSR is set to 1. The PORF bit is a read-only register that can be initialized only by resetting the
pin. Figure 4.2 shows the operation of the power-on reset.
1
Vpor*
External
power supply
Vcc
RES pin
Power-on reset
signal (enabled
when in low state)
Internal reset
2
signal *
(enabled
when in low state)
PORF
(logical value)
Note: For details on the electrical characteristics, see section 28, Electrical characteristics.
1 . Vpor indicates the level of the power-on reset detection.
2. The internal reset signal initializes the internal state of bits other than the bit PORF
and the state of the pins.
3. T
indicates the power-on reset time.
por
Rev. 1.00 May 09, 2008 Page 84 of 954
REJ09B0462-0100
Reset state
3
*
T
por
Set
Figure 4.2 The Operation of the Power-On Reset
Reset state
3
*
T
por
Set
Reset state
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