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2
Section 17 I
C Bus Interface (IIC)
Start condition generation
SCL
(Pin waveform)
SCL
(Master output)
SCL
(Slave output)
SDA
(Master output)
SDA
(Slave output)
IRIC
ICDRF
ICDRS
ICDRR
User processing
[2] ICDR read
Figure 17.14 Example of Slave Receive Mode Operation Timing (1) (MLS = 0)
[7] SCL is fixed low until ICDR is read
SCL
8
(Master output)
SCL
(Slave output)
SDA
Bit 0
(Master output)
Data (n-1)
SDA
(Slave output)
IRIC
ICDRF
ICDRS
Data (n-1)
Data (n-2)
ICDRR
User processing
[8] IRIC clear
[9] Set ACKB=1
Figure 17.15 Example of Slave Receive Mode Operation Timing (2) (MLS = 0)
Rev. 1.00 May 09, 2008 Page 534 of 954
REJ09B0462-0100
1
2
3
1
2
3
Bit 7 Bit 6
Bit 5
Slave address
Undefined value
9
1
2
3
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[6]
Data (n)
A
Data (n-1)
[5] ICDR read (Data (n-1))
[7] SCL is fixed low until ICDR is read
4
5
6
7
8
4
5
6
7
8
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W
[8] IRIC clear
[7] SCL is fixed low until ICDR is read
4
5
6
7
8
Data (n)
[8] IRIC clear
9
1
2
9
1
2
Bit 7 Bit 6
Data 1
[6]
A
Interrupt
request
occurrence
Address+R/W
Address+R/W
[10] ICDR read (dummy read)
Stop condition
generation
9
[6]
[11]
A
Data (n)
[10] ICDR read
[12] IRIC clear
(Data (n))
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